1. Field of the Invention
This invention relates to a pulse width modulation device with a power saving mode controlled by an output voltage feedback hysteresis circuit. In particular, this invention relates to a pulse width modulation device used in a power supply that controls the output driving signal according to the output load variation.
2. Description of Related Art
In the applications of low power output, such as a charger for a mobile phone, a wireless telephone, a digital still camera and a PDA, and an AC voltage regulator for a printer, a TV game player, and a hand-held Walkman, has great request for power saving in a standby mode.
In currently known DC power supply devices, such as an AC-to-DC switching power supply, in order to reduce the volume of a transformer, a high-frequency pulse width modulation PWM is widely used to control a DC output voltage, as shown in FIG. 1, which is a structure diagram of the circuit of a conventional flyback power supply device. The circuit is divided into a pre-stage circuit 101 of primary side and a post-stage circuit 102 of secondary side by a transformer T1. A phototransistor 111 and a photodiode 112 are provided between the primary side 101 and the secondary side 102 to separate an electrical signal at the primary side 101 from that at the secondary side 102. However, an optical signal can be used to feed a voltage or output current variation signal at the secondary side 102 back to the primary side 101 so as to synchronously adjust the variable quantity of voltage or current at the primary side 101 or the secondary side 102. This output signal is also used as a feedback signal for over current or short circuit protection.
Please refer to FIG. 1 again. From the primary side 101, an AC voltage VAC is inputted that passes through an EMI filter 1010, a bridge rectifier BD1, and a high voltage filter capacitor C1 to transform a DC voltage Vin. Through a pulse regulation control unit U1 controls the turn-on period of a power transistor switch Q1, the DC voltage Vin is transmitted to the primary-side winding of transformer T1. In the mean time, the secondary-side winding of transformer T1 induces an output voltage, and after being rectified and filtered by a diode D1 and an electrolysis capacitor C2, the voltage is transformed into a stable DC voltage Vout and outputted.
The outputted DC voltage Vout is transformed into a voltage signal VFB via a feedback voltage regulator D3 and an optical coupler 11, and then fed back to the pulse regulation control unit U1 at the primary side 101. At the same time, when the power transistor switch Q1 turns ON, a detecting current signal Vcs is obtained via a resistor R2 and sent to the control unit U1. The unit U1 gets the signal Vcs and the voltage signal VFB to calculate and output a PWM to the switch Q1 for stabilizing of the outputted DC voltage Vout. The optical coupler 11 is composed of the phototransistor 111 and the photodiode 112.
Please refer to FIG. 2, which shows a block diagram of the circuit of a conventional pulse width modulation control unit. The pulse width modulation control unit U1 is composed of a PWM comparator 14, an overcurrent comparator 16, a flip-flop 18, and OR gates. The operation method of PWM is described as below. An oscillating circuit 12 provides a fixed frequency clock PWMclock to the pulse regulation control unit U1. Further, the PWM comparator 14 in the pulse regulation control unit U1 detects the voltage signal VFB fed back from the outputted DC voltage Vout and detects the current signal Vcs to compare for outputting a modulation output signal PWMout. The overcurrent comparator 16 further obtains the detecting current signal Vcs and a current limiting level 1V to execute a comparison operation for outputting an over current enable signal OCPEN. After the modulation output signal PWMout and the overcurrent enable signal OCPEN are logically operated via the of OR gates, a reset signal R is outputted to the port R of the flip-flop 18. The port S of flip-flop 18 is connected to an oscillating circuit 12 to obtain a fixed frequency clock PWMclock that is used as an operating frequency, and outputs a drive signal Drv to a power switch (not shown in the figure) after logically operated by OR gates and a NOT gate.
Please refer to FIGS. 2 and 3. FIG. 3 shows signal waveforms given from the conventional pulse width modulation control unit. In FIG. 3, the abscissa axis is an axis of time t and the ordinate axis shows all waveforms. During the period of time t0 to t1, the voltage signal VFB is indicate a heavy-load signal, and after the modulation output signal PWMout and the overcurrent enable signal OCPEN are logically operated by of the OR gates, a reset signal R is outputted to make an output pulse width of the drive signal Drv outputted by the flip-flop 18 wider. In other words, the duty cycle of the power switch (not shown in the figure) becomes longer. Thereby, the electric power for the load is provided.
Likewise, during the period of time t1-t2, a normal load exists and the width of pulse of the drive signal Drv outputted by the flip-flop 18 is belonging to a width of the normal power supply. Then, the load becomes lighter during the period of time t2-t3. After the modulation output signal PWMout and the overcurrent enable signal OCPEN are logically operated by the OR gates to output a reset signal R. The reset signal R and the fixed frequency clock PWMclock outputted from the oscillating circuit 12 are calculated by the flip-flop 18, the output pulse width of the drive signal Drv outputted from the flip-flop 18 becomes shorter. Thereby, an electric power for the light load is provided. The operating frequency of the power switch (not shown) driven by the drive signal Drv does not vary with the variation of duty cycle of output pulse. In other words, the operating frequency of the circuit is permanently fixed. Therefore, in the condition of light load, the drive signal Drv constantly generates a pulse with a short duty cycle that depends on the clock PWMclock. Thereby, the power consumption is wasted in the condition of light load. At the period of t3-t4, the circuit is in the condition of no load, and no drive signal Drv is outputted. This period is a skipped cycle.
When an electronic product works in the condition of full load or medium load, it usually controls the switching operation of a switch by PWM. Its working loss includes a conduction loss and a switching loss. However, when the electronic product is in the condition of light load or no load, if the PWM is still used for controlling the switching operation of the switch, the conduction loss decreases due to the electronic product is in the condition of light load. However, because the operating frequency of the switch is constantly fixed, the switching loss does not decrease with the load decreasing. Therefore, in the condition of light load, the operation mode by using the PWM will decease the efficiency of the whole system.
Please refer to FIG. 4, which shows a block diagram of a conventional oscillating circuit. The oscillating circuit 12 utilizes a voltage source VDD to supply the electric power to the voltage-dividing resistors R1, R2, and R3 to provide the set of threshold voltage VH and VL. Then, the comparators 121 and 122 individually obtain the set of threshold voltage VH and VL and compare the charge and discharge signals outputted by a capacitor CT. After being operated, the signals adjust control current sources I1 and I2 via a flip-flop 123 to charge and discharge the capacitor CT. Then, the oscillating circuit 12 generates the clock PWMclock at an output terminal Q of the flip-flop 123 to supply a reference frequency for the PWM.